Traditionally, manufacturers test memory within memory systems at the time of manufacture in order to detect defects within the memory. One way in which manufacturers test memory for defects is to subject the memory to a number of operations in order to bring out defects in the memory. For example, causing significant stress in a memory may result in errors becoming evident such as a strong or weak control gate substrate short (“CGSS”), a wordline-to-wordline short, and/or a broken wordline within the memory of the storage system.
While the above-described procedure may allow manufacturers to detect defects within the memory, applying enough stress to the memory in order to bring out the defects may cause the memory to become vulnerable to more failures causing a loss of memory yield. Therefore, improved systems and methods for detecting defects within a memory that do not reduce an overall memory yield are desirable.